Memory subsystem voltage control and method

ABSTRACT

A method and apparatus for providing a preferred operating voltage to a memory device as specified by a stored configuration parameter. The apparatus includes a nonvolatile memory configured to store a preferred memory device voltage configuration corresponding to a preferred operating voltage of the memory device. The preferred memory device voltage configuration is readable by a host and the circuit is responsive to a command to modify the voltage to the memory device in accordance with the preferred memory device configuration. The voltage to the memory device is modified for improved performance and compatibility of the memory device with a host system.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to computer system memories and,more particularly, to controlling operating voltage provided to memorydevices.

[0003] 2. State of the Art

[0004] Computer systems are typically designed to accommodate memorydevices that perform within a specific band of operational parameters.For example, a computer design may accommodate specific memory devicesthat perform reading and writing operations at a defined speed or rate.Such an interdependent design philosophy disregards many realities ofthe environment of a computer system over its lifetime. For example,designing for a specific performance relationship between amicroprocessor and memory devices does not allow for the independentimprovements to each of the components that may, and generally does,occur. For example, microprocessor speeds may outpace memory deviceperformance, or vice versa. In an attempt to decouple such arelationship, memory controllers have been designed to provide databrokering between the microprocessor and the memory device. Once memorycontrollers became ubiquitous in computer system designs, broadvariations in memory device performance parameters have becomecommonplace.

[0005] Additionally, memory devices are generally tested and gradedduring manufacturing, with similarly performing devices integratedtogether into independent memory modules. As technology advances or as acomputer system's memory needs change, memory modules may be upgraded orexchanged within a computer system. When memory modules are added,replaced, or exchanged with other memory modules, the memory controlleradapts the timing between the memory modules and the microprocessor.

[0006] To date, the adaptation between the memory modules and the memorycontroller has been limited to modifications in timing and controlparameters. However, it is known that memory technology improvementshave also been made which have resulted in changes to improved oroptimal operational voltages of the memory devices. Memory devicesoperating at a modified voltage level may exhibit an improvement inperformance. Adaptation of such parameters has not been addressed by theprior art.

BRIEF SUMMARY OF THE INVENTION

[0007] The present invention comprises a method and circuit forconfiguring a memory device operating voltage in a system in accordancewith a preferred memory device voltage configuration stored inconjunction with the deployment of the memory device. A preferredoperating voltage for one or more memory devices is determined andstored as a preferred memory device voltage configuration in nonvolatilestorage associated with the memory device. In one embodiment, the memorydevice and the nonvolatile memory having the preferred voltageconfiguration stored therein co-reside on a memory module. When thememory module is hosted by a computer system, the preferred memorydevice voltage configuration is read and commands generated formodifying the voltage supplied to the memory device.

[0008] The present invention also comprises an electronic system andcomputer system embodiments incorporating the circuitry and method. Inthe system embodiments, a processor coupled to a memory module includingone or more memory devices and the nonvolatile memory reads thepreferred memory device voltage configuration and generates commands tobias the memory device voltage.

[0009] The present invention further includes a method for testing theoperation range of a memory device using a reprogrammable nonvolatilememory device configured in accordance with an embodiment of the presentinvention.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0010] In the drawings, which illustrate what is currently considered tobe the best mode for carrying out the invention:

[0011]FIG. 1 is a system block diagram of a computer system, inaccordance with an embodiment of the present invention;

[0012]FIG. 2 is a diagram of a memory system according to an embodimentof the present invention;

[0013]FIG. 3 is a block diagram of a memory module configured inaccordance with an embodiment of the present invention;

[0014]FIG. 4 is a memory map of a nonvolatile memory configured inaccordance with an embodiment of the present invention; and

[0015]FIG. 5 is a flowchart illustrating voltage modifications to memorydevices, in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0016]FIG. 1 illustrates a block diagram of a computer configured inaccordance with an embodiment of the present invention. The computer 10includes a processor 12 which is further connected to a high speed hostbus 14 configured in a manner appreciated by those of ordinary skill inthe art. Host bus 14 further couples to one or more logic devices (e.g.,a system core logic chip set), a portion of which is illustrated asmemory controller 16 and bus bridge 18. Memory controller 16 and busbridge 18 may be from a chip set, such as a Triton VX chip by IntelCorporation of Santa Clara, Calif. Memory controller 16 includes memorymapping logic for mapping processor 12 addresses to a particular addressbase in system memory 20.

[0017] System memory 20 comprises a random access memory (RAM) residenton one or more memory modules such as a dual in-line memory module(DIMM), single in-line memory module (SIMM), RAMBUS® in-line memorymodule (RIMM) and Triple in-line memory module (TRIMM) as well asothers. In an exemplary embodiment, the memory module or modules,detailed below in FIG. 2, each further include an electronicallyreadable nonvolatile memory which identifies a particular preferredvoltage configuration corresponding to a preferred operating voltage,for example V_(DD), V_(DDQ) and/or V_(ref), of at least one memorydevice on the corresponding memory module.

[0018] System memory 20 is further connected to a low speed bus 22 whichmay be implemented as a serial bus such as a System Management (SM) busor an I² C bus. In the exemplary embodiment, the nonvolatile memory ofsystem memory 20 is accessed using the low speed bus 22. Low speed bus22 is managed by a low speed bus master 24 which interfaces withprocessor 12 via a high speed I/O bus 26, an example of which is a PCIbus. The low speed bus master 24 may be implemented as an SM buscontroller which forms a portion of, for example, a PIIX4 chip by IntelCorporation.

[0019] Computer 10, in accordance with an embodiment of the presentinvention, further includes a power converter 28 which provides anadjustable power, in the form of voltage and current, to system memory20. Power converter 28 generates memory operating voltage 36 foroperation of system memory 20. In an exemplary embodiment, powerconverter 28 operates initially under a default voltage configuration,illustrated in FIG. 1 as default voltage configuration 68. While theconfiguration and operation of power converter 28 may be alteredaccording to various circuits, a preferred implementation couples avoltage bias to modify or set the memory operating voltage to apreferred operating voltage.

[0020] In a preferred embodiment, a power converter bias 38 isgenerated, in part, by processor 12 reading a preferred memory devicevoltage configuration 58 (FIG. 3) via the low speed bus 22. Processor 12generates a digital command and sends the command via the low speed bus22 to a digital-to-analog converter (DAC) 30 which, in turn, generates apower converter bias 38 to cause the power converter 28 to modify memoryoperating voltage 36 to a preferred operating voltage, as specific bythe preferred memory device voltage configuration 58 (FIG. 3). Asillustrated, low speed bus 22 is coupled to the high speed I/O bus 26via a low speed bus master or controller 24 as used for the support oflow speed peripherals, such as for the accessing of the nonvolatilememory within system memory 20 as well as for the interaction with theDAC 30 which provides a biasing signal 38 to power converter 28.

[0021] Computer 10 further includes input devices 32 which may coupledirectly or indirectly with the high speed I/O bus 26, in one or morevarious configurations known to those of ordinary skill in the art.Similarly, output devices 34 also couple to high speed I/O bus 26 ineither a direct or indirect manners also known to those of ordinaryskill in the art.

[0022]FIG. 2 is a block diagram of the system memory 20, in accordancewith an exemplary embodiment of the present invention. System memory 20may have multiple and different organizations including multiple socketsfor receiving multiple memory modules. The system memory 20 may also beconfigured to include a variety of memory module types and may furtherinclude discrete chips directly mounted on a motherboard. The memorycontroller 16 may be set to one of multiple configurations to interfaceto the different memory organizations. FIG. 2 illustrates one exemplarymemory organization including four individual memory modules 40A, 40B,40C, and 40D. Memory modules 40 may assume the form of various moduleconfigurations such as DIMM, SIMM, RIMM, TRIMM or other defined moduleconfigurations. In addition, different types of DIMM modules may beused, such as DIMM configurations having enhanced data output (EDO)DRAMs or DIMM configurations having SDRAMs. Furthermore, the DIMMconfigurations may be single-sided or double-sided. As illustrated, eachmemory module 40A-40D includes one or more memory devices 48 whichprovide the general storage memory accessible by memory controller 16over a memory control and data bus 50.

[0023] Each memory module 40A-40D receives operational voltage,illustrated as memory operating voltage 36, from power converter 28(FIG. 1) via a socket contact or other interconnecting signal, notshown. The magnitude of memory operating voltage 36 may be altered inaccordance with the process of the present invention in order to providean improved voltage to each of the memory devices 48 of memory modules40A-40D.

[0024] One or more of memory modules 40A-40D further include anonvolatile memory 52 which is accessible by the low speed bus 22.Nonvolatile memory 52 may be in the form of read only memory (ROM) ormay be in the form of a rewritable and randomly accessible memorydevice. Those of ordinary skill in the art appreciate the various typesof nonvolatile memory devices including Programmable ROM (PROM),Electronically Erasable PROM (EEPROM), Flash memory as well as others.

[0025]FIG. 3 illustrates an exemplary memory module 40 having anarchitecture in accordance with a preferred embodiment of the presentinvention. The memory module 40 includes a memory space 56 which isaccessed via a memory control and data bus 50. The memory module 40includes the electronically readable nonvolatile memory 52 which furtherincludes a memory device voltage configuration 58 in a designated spacewithin nonvolatile memory 52. Nonvolatile memory 52 is accessed via thelow speed bus 22, illustrated in FIG. 3 as a serial bus including a datasignal 60 and a clock signal 62. Exemplary implementations of low speedbus 22 include I²C or SM bus configurations, whose implementations arereadily available or, alternatively, may be obtained from theirrespective sponsors, namely Phillips Corporation and Intel Corporation.

[0026]FIG. 4 illustrates the address space of nonvolatile memory 52, inaccordance with an exemplary embodiment of the present invention.Nonvolatile memory 52 has an address space which is divided into vendorused and unused areas. In the preferred embodiment, nonvolatile memory52 includes 256 bytes, from byte 0 to byte 255. The first 128 bytes,byte 0 to byte 127, define a first address space 64 which is used by thevendor for storing vendor-supplied information. The first address space64 is typically organized in accordance with a standard body, such asthe Joint Electronic Devices Engineering Counsel (JEDEC) standard. Asillustrated in FIG. 4, the first address space 64 may be furtherreferred to as the JEDEC area or memory space and typically includes atleast one additional memory device configuration 80 for facilitatinginteraction between the system memory 20 (FIG. 1) and the processor 12(FIG. 1) by appropriately configuring the timing or some other interfaceparameter within memory controller 16 (FIG. 1). Also illustrated in FIG.4 is a second or undefined address space 66 which is utilized forstoring the memory device voltage configuration 58, in accordance withthe present invention.

[0027] An aspect of the present invention uses the memory device voltageconfiguration 58 to identify a preferred operating voltage, illustratedas memory operating voltage 36 (FIG. 1), that enables improved oroptimal performance by the memory devices 48 (FIG. 3) logically locatedwithin memory space 56 (FIG. 3). Through the use of an analysis processprogrammed within processor 12, a power converter bias 38 (FIG. 1) iscalculated from the memory device voltage configuration 58 and therespective commands are sent via the low speed bus 22 to a DAC 30 forthe generation of the power converter bias 38.

[0028] The method of implementing memory module voltage adjustments isillustrated in FIG. 5 with further reference to the specific elements ofFIG. 1. Initially, computer 10 and the individual components such asprocessor 12, undergo power-on processes. According to an exemplaryembodiment of the present invention, power is applied to the variouscomponents of system or computer 10 with a default voltage configuration68 in an act 70 providing an initial bias or conditions for directingpower converter 28 to generate memory operating voltage 36 to facilitateadequate voltage to the nonvolatile memory during a configurationprocess. FIG. 1 illustrates one embodiment in which such an applicationof default voltage may occur. As illustrated in FIG. 1, the defaultvoltage configuration 68 may be applied directly to power converter 28,causing the generation of a default voltage to be present at memoryoperating voltage 36. Alternatively, a default voltage configuration 68may be applied, as illustrated in the dashed lines of FIG. 1, to thedigital-to-analog converter 30. In such an initialization configuration,system memory 20 allows voltage to be applied to the nonvolatile memory52 (FIG. 2) in order to enable the reading of the nonvolatile memory inan act 72.

[0029] Once the memory module is powered according to the default powerconfiguration, an act 72 reads the nonvolatile memory 52 (FIG. 2) andretrieves memory device configuration information. Memory deviceconfiguration 80 (FIG. 4) is forwarded to the memory controller 16 forconfiguring the timing and control for appropriate accessing of thememory device. A query act 74 determines the presence of a memory devicevoltage configuration 58 (FIG. 4) and, when present, returns thepreferred memory device voltage configuration 58 for evaluation byprocessor 12. A command is generated in a manner capable of altering orotherwise modifying the memory module voltage. In an exemplaryembodiment as illustrated in FIG. 1, a power bias is generated in an act76 and is passed via the low speed bus 22 to the digital-to-analogconverter 30. The digital-to-analog converter 30 generates the powerconverter bias 38 which, in turn, in an act 78 modifies the powerparameters of memory operating voltage 36 as sent to the memory moduleswithin system memory 20. Following such adjustments to memory modulevoltage, the method for modifying the voltage sent to the memory modulesconcludes and any other initialization steps may be subsequentlyperformed by processor 12.

[0030] Although the foregoing description contains many specifics, theseshould not be construed as limiting the scope of the present invention,but merely as providing illustrations of some exemplary embodiments.Similarly, other embodiments of the invention may be devised which donot depart from the spirit or scope of the present invention. Featuresfrom different embodiments may be employed in combination. The scope ofthe invention is, therefore, indicated and limited only by the appendedclaims and their legal equivalents, rather than by the foregoingdescription. All additions, deletions, and modifications to theinvention, as disclosed herein, which fall within the meaning and scopeof the claims are to be embraced thereby.

What is claimed is:
 1. A memory module, comprising: at least one memorydevice configured to operate at a preferred operating voltage; and anonvolatile memory configured to store a preferred memory device voltageconfiguration designating said preferred operating voltage of said atleast one memory device.
 2. The memory module, as recited in claim 1,further comprising a first memory bus for interfacing with said at leastone memory device and a second bus for interfacing with said nonvolatilememory.
 3. The memory module, as recited in claim 2, wherein said secondbus is a serial bus.
 4. The memory module, as recited in claim 3,wherein said serial bus is configured in accordance with one of an SMbus and an I² C bus standards.
 5. The memory module, as recited in claim1, wherein said nonvolatile memory is further configured to store atleast one additional memory device configuration parameter to facilitateinteraction with said at least one memory device.
 6. The memory module,as recited in claim 1, wherein said nonvolatile memory is reprogrammableto store at least a first voltage configuration to test said memorymodule and said preferred memory device voltage configuration.
 7. Thememory module, as recited in claim 1, wherein said memory module isconfigured as one of a DIMM, SIMM, RIMM and TRIMM module.
 8. Anelectronic system, comprising: a processor; at least one of an inputdevice and an output device operably coupled to said processor; and amemory module operably coupled to said processor, said memory moduleincluding: at least one memory device configured to operate at apreferred operating voltage; and a nonvolatile memory configured tostore a preferred memory device voltage configuration designating saidpreferred operating voltage of said at least one memory device.
 9. Thesystem, as recited in claim 8, further comprising a first memory busoperably coupling said processor with said at least one memory deviceand a second bus operably coupling said processor with said nonvolatilememory.
 10. The system, as recited in claim 9, wherein said second busis a serial bus.
 11. The system, as recited in claim 10, wherein saidserial bus is configured in accordance with one of an SM bus and an I²Cbus standards.
 12. The system, as recited in claim 8, further comprisinga memory controller operably coupled between said processor and saidmemory module and wherein said nonvolatile memory is further configuredto store at least one additional memory device configuration parameterto configure said memory controller for operably interfacing with saidat least one memory device.
 13. The system, as recited in claim 8,wherein said nonvolatile memory is reprogrammable to store at least afirst voltage configuration to test said memory module and saidpreferred memory device voltage configuration.
 14. The system, asrecited in claim 8, wherein said memory module is configured as one of aDIMM, SIMM, RIMM and TRIMM module.
 15. A computer system, comprising: aprocessor; a memory module including at least one memory deviceconfigured to retain information as directed by said processor and tooperate at a preferred operating voltage, said memory module furtherconfigured to store both a preferred memory device voltage configurationdesignating said preferred operating voltage of said at least one memorydevice and at least one additional memory device configurationparameter; and a memory controller operably coupled between saidprocessor and said memory module and configured for operably interfacingsaid at least one memory device with said processor according to said atleast one additional memory device configuration parameter.
 16. Thecomputer system, as recited in claim 15, wherein said memory modulefurther comprises a nonvolatile memory configured to store saidpreferred memory device voltage configuration and said at least oneadditional memory device configuration parameter.
 17. The computersystem, as recited in claim 16, further comprising a serial bus operablycoupling said processor with said nonvolatile memory.
 18. The computersystem, as recited in claim 17, wherein said serial bus is configured inaccordance with one of an SM bus and an I²C bus standards.
 19. Thecomputer system, as recited in claim 16, wherein said nonvolatile memoryis reprogrammable to store at least a first voltage configuration totest said memory module and said preferred memory device voltageconfiguration.
 20. The computer system, as recited in claim 15, whereinsaid memory module is configured as one of a DIMM, SIMM, RIMM and TRIMMmodule.
 21. A circuit, comprising: a nonvolatile memory configured tostore a preferred voltage configuration readable and interpretable by aprocessor; at least one memory device having a preferred operatingvoltage as designated by said preferred voltage configuration, said atleast one memory device further configured to operably couple with saidprocessor; and a power converter operably coupled to said at least onememory device to provide said preferred operating voltage to said atleast one memory device in response to said processor and said preferredvoltage configuration.
 22. The circuit, as recited in claim 21, whereinsaid nonvolatile memory and said at least one memory device arecollocated on a memory module.
 23. The circuit, as recited in claim 21,further comprising a first memory bus for interfacing with said at leastone memory device and a second bus for interfacing with said nonvolatilememory.
 24. The circuit, as recited in claim 23, wherein said second busis a serial bus.
 25. The circuit, as recited in claim 24, wherein saidserial bus is configured in accordance with one of an SM bus and an I²Cbus standards.
 26. The circuit, as recited in claim 21, wherein saidnonvolatile memory is further configured to store at least oneadditional configuration parameter to facilitate interaction with saidat least one memory device.
 27. The circuit, as recited in claim 22,wherein said memory module is configured as one of a DIMM, SIMM, RIMMand TRIMM module.
 28. The circuit, as recited in claim 21, furthercomprising a digital-to-analog converter operably coupled to said powerconverter and configured to receive a bias configuration signal inresponse to said preferred voltage configuration.
 29. A method forproviding a preferred operating voltage to a memory module having atleast one memory device thereon, comprising: reading a preferred memorydevice voltage configuration from said memory module, said preferredmemory device voltage configuration identifying a preferred operatingvoltage of said at least one memory device; and generating, in responseto said preferred memory device voltage configuration, a voltage bias toadjust voltage provided to said memory module to said preferredoperating voltage.
 30. The method, as recited in claim 29, wherein saidreading comprises reading said preferred memory device voltageconfiguration from a nonvolatile memory on said memory module.
 31. Themethod, as recited in claim 29, wherein said generating comprisesconverting said preferred memory device voltage configuration into acommand for generating a power bias causing voltage provided to saidmemory module to be said preferred operating voltage.
 32. The method, asrecited in claim 31, wherein said converting comprises converting saidpreferred memory device voltage configuration into a command directed toa digital-to-analog converter to generate said power bias to cause apower converter to in turn generate said preferred operating voltage tosaid at least one memory device on said memory module.
 33. The method,as recited in claim 29, wherein said reading includes reading apreferred memory device voltage configuration over a serial bus.
 34. Themethod, as recited in claim 32, wherein said serial bus is configured inaccordance with one of an SM bus and an I²C bus standards.
 35. Themethod, as recited in claim 29, further comprising coupling a memorycontroller between a processor and said memory module and wherein saidnonvolatile memory is further configured to store at least oneadditional memory device configuration parameter to configure saidmemory controller for operably interfacing with said at least one memorydevice.
 36. The method, as recited in claim 29, further comprising:programming at least a first voltage configuration to test said memorydevice into said memory module; and reprogramming and said preferredvoltage configuration into said memory module.
 37. The method, asrecited in claim 29, wherein said memory module is configured as one ofa DIMM, SIMM, RIMM and TRIMM module.
 38. A method for testing anoperational range of a memory module, comprising: storing a first memorydevice voltage configuration within a nonvolatile memory device on saidmemory module, said first memory device voltage configurationidentifying a first testing voltage of at least one memory deviceresident on said memory module; reading said first memory device voltageconfiguration from said nonvolatile memory; and generating, in responseto said first memory device voltage configuration, a power bias toadjust voltage provided to said memory module to said first testingvoltage.
 39. The method, as recited in claim 38, wherein said generatingcomprises converting said first testing voltage configuration into acommand for generating a power bias and modifying voltage provided tosaid memory module to said first testing voltage.
 40. The method, asrecited in claim 38, further comprising reprogramming said nonvolatilememory with a preferred memory device voltage configuration identifyinga preferred operating voltage of said at least one memory device.
 41. Acomputer-readable media including computer-executable instructions forproviding a preferred operating voltage to a memory module having atleast one memory device thereon, the computer-executable instructionscomprising: reading a preferred memory device voltage configuration fromsaid memory module, said preferred memory device voltage configurationidentifying a preferred operating voltage of said at least one memorydevice; and generating, in response to said preferred memory devicevoltage configuration, a power bias to adjust voltage provided to saidmemory module to said preferred operating voltage.
 42. Thecomputer-readable media having computer-executable instructions thereon,as recited in claim 41, wherein said computer-executable instruction forreading comprises computer-executable instructions for reading saidpreferred memory device voltage configuration from a nonvolatile memoryon said memory module.
 43. The computer-readable media havingcomputer-executable instructions thereon, as recited in claim 41,wherein said computer-executable instruction for generating comprisescomputer-executable instructions for converting said preferred memorydevice voltage configuration into a command for generating a power biascausing voltage provided to said memory module to be said preferredoperating voltage.
 44. The computer-readable media havingcomputer-executable instructions thereon, as recited in claim 43,wherein said computer-executable instruction for converting comprisescomputer-executable instructions for converting said preferred memorydevice voltage configuration into a command directed to adigital-to-analog converter to generate said power bias to cause a powerconverter to in turn generate said preferred operating voltage to saidat least one memory device on said memory module.
 45. Thecomputer-readable media having computer-executable instructions thereon,as recited in claim 41, wherein said computer-executable instruction forreading includes computer-executable instructions for reading apreferred memory device voltage configuration over a serial bus.